Correctness of Transformations in High Level Synthesis : Formal Veri cation

This paper presents a formal approach to address the correctness of transformations in high-level synthesis. The novelty of the work is that a small set of properties that capture a general notion of reenement of control/data-ow graphs used in an industrial synthesis framework have been given, and the properties are independent of the underlying behavior model. We have mechanized the speciication and veriication of several optimization and reenement transformations used in industrial hardware design. This work has enabled to nd and rectify errors in the transformations. Further, the work has led to generalization of transformations typically used in high-level synthesis.